An 80 MHz computer clock oscillator is used to drive a step-recovery diode, generating copious odd-harmonic output. The harmonic at 5760 MHz (or thereabout) is quite strong. A 3-pole microstrip filter isolates only the harmonics in that region.
Following the filter is another MMIC amplifier, and a 5-pole microstrip
filter. The final filter effectively isolates only the desired harmonic
(others are more than 40 dB down). The filter output is both isolated and
amplified by a final MMIC stage up to the 0 dBm level, which drives the
final amplifier stage.
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64 MHz |
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80 MHz |
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418.0 |
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1440.0 |
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I don't think my design has all these components--and that may be why it doesn't work.
Question--why did my first SRD multiplier -- an oscillator feeding an SRD, coupled by a capacitor -- work so well? How did the "pipecap filter" transmitter work?
I have some idea about the pipecap transmitter. I think the pipcap served as a nice resonator for the SRD. Also, I think I used three stages of amplification, one of which was the MMIC-of-doom, the MGA-86576.
The circuit has three functions:
In addition, the circuit has a transmit disable input (TXDIS), which
disables the MOD80MHZ output.
The BEACONPULS input allows the circuit to be triggered by the transponder's
microprocessor instead of the receiver, to create regularly spaced beacon
pulses which aid in finding the transponder.
(Note: Set browser width so that the following ASCII figure has a box around it.)
TSS CALCULATION with PRE-DETECTION GAIN
¦------------------------------------------------------------------------------¦
¦
¦
¦
¦\
¦\
¦
¦ RF amplifier
¦__\ Detector
¦__\ Video Amplifier ¦
¦
¦____\
¦____\
¦
¦ In o----------¦_____>----------------------¦_____>--------o
Out ¦
¦
¦____/ ¦
¦____/
¦
¦
¦__/ +---+
¦__/
¦
¦
¦/
¦/ \¦
¦/
¦
¦
+---+
¦
¦ Gain
32.0 dB
¦
¦
¦ N.F.
1.9 dB
----- N.F.
4.0 dB
¦
¦ Bandwidth 80.000 x
10^6 Hz --- Bandwidth
10.000 x 10^6 Hz ¦
¦
¦
¦------------------------------------------------------------------------------¦
¦ Enter either:
¦ Or:
¦
¦ Detector mV/mW =
0.0 and Ohms = 0.0 ¦ Quality factor
= 245.97 ¦
¦------------------------------------------------------------------------------¦
¦
<<< Calculated TSS = -83.48802 dBm. >>>
¦
+------------------------------------------------------------------------------+
RF amplifier is a composite of two stages:
| MGA-86576 | ERA-2 | COMPOSITE | |
| NF (@ 6 GHz) | 1.8 | 6.5 | 1.95 |
| Gain (@ 6 GHz) | 18 | 14 | 32 |
The pre-detector bandwidth limitation is provided by the patch antenna itself.
The equation is: (from Jasik's Antenna Handbook)
BW = 4 f^2 (t / (1/32))
f in GHz
BW in MHz
t is board thickness, in inches.
Detector is a voltage doubler based on HP HSMS-2852 dual zero-bias detector,
which is
desirable w/r/t cost (0.91 each). Prototype will probably use
(2) Alpha DDC254-250's
are on hand but have differing characteristics.
Detector figure of merit:
M = B/(r)^.5
Where B
is detector sensitivity in volts/watt
r is detector effective source resistance
M= 245.97 for the HP HSMS-2852 (notice the doubled value is used above, since it's a voltage doubler.)
The calculation is based on the work of W. J. Lucas, as reported
in
Proceedings of the IEEE, 113, 1321-1330 (1966).
The specific form of the equations used is that presented by
James B.
Tsui, in his book Microwave Receivers with EW Applications,
Published
by John Wiley and Sons.
The video amplifier is as of yet undetermined, but a 4 dB NF was guessed.