Nov 7, 1998

The advantages of using SPI instead of a parallel data bus to transfer data in
the DARTS interrogator are obvious: lower wire count, lower radiated noise,
easier routing between boards.  However, I originally had concerns that the
transfers were fast enough to support real-time data.  This study allays those
trepidations.

5 MHz is maximum SPI transfer rate on PIC16C7x processor.  At this rate, a byte
takes 1.6 uS.  For a range or ADC transfer, two bytes are required, totalling
3.2 uS per transfer.

Since SPI support is rare in flash or subranging ADCs, an external shift
register is required. With the lower interconnect count of SPI, it makes sense
to put the ADC into the log amp's enclosure, ensuring that the high-speed shift
register is properly enclosed.

Also, there are no high-speed counters available with SPI-interfaced output
latches.  Previously, I had used the 74HC590, which has an internal parallel
capture register.  This part is becoming harder to find, so SPI support is a
good excuse to go to a more popular high-speed 8-bit counter (such as a 74F286?)
with an external parallel to serial converter that is latched on transmit/
receive transitions.

All that SPI means for the motion control circuit is that writing bytes takes
1.6 uS now instead of 200 nS (the instruction rate at 20 MHz).

For ease of interfacing and lowering of signal count, SPI makes good sense.
However, analysis is required to ensure that real-time data rates can be
supported.

Below is a pseudocoded algorithm for the antenna sampling interrupt routine. The
4-position RF switch on the reciver input is switched to each of the four
antenna positions, and the resulting IF voltage is acquired.  The SPI tranfers
are interleaved with the switching and conversion to save time.  As switching
and latching operations are single instructions cycle operations.

cvt #1
wait 1 us
sw #2
latch #1
xfer #1-lsb (1.6 uS per byte)
cvt #2
xfer #1-msb
sw #3
latch #2
xfer #2-lsb
cvt #3
xfer #2-msb
sw #4
latch #3
xfer #3-lsb
cvt #4
xfer #3-msb
sw back to #1
(pulse can be ended now)
latch #4
xfer #4-lsb
xfer #4-msb
 

Total required pulse width: 10.6 uS
Longer is desirable for PWM decoding

This shows that SPI serial transfer of ADC data is entirely possible with ADC
resolutions of up to 16 bits.